1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device using split gate transistors.
2. Description of the Related Art
Recently, great attention is being paid to non-volatile semiconductor memory devices that include a Ferro-electric Random Access Memory, EPROM (Erasable and Programmable Read Only Memory) and EEPROM (Electrically Erasable and Programmable Read Only Memory). In the EPROM and EEPROM, charges are stored in the floating gate electrode as data, and this data is read by detecting a change in threshold voltage depending on the presence or absence of the charges by means of the control gate electrode. The EEPROM includes a flash EEPROM that can collectively erase data in the whole memory cell array or can partially erase data, block by block, from the memory cell array separated to an arbitrary number of blocks.
A plurality of memory cells (or memory transistors) constituting a flash EEPROM are classified to two types: stacked gate type and split gate type. In a flash EEPROM using stacked gate memory cells, each memory cell cannot self-select its own ON/OFF state. If charges are excessively drained from the floating gate electrode at the time of data erasure, therefore, the channel region becomes conductive even when a predetermined voltage (e.g., 0 V) for rendering each memory cell non-conductive is applied to the control gate electrode. As a result, that memory cell always becomes conductive, thus causing the so-called excess erasure by which reading of stored data is disabled. To prevent this excess erasure, the erasing procedures of the individual memory cells should be controlled by a peripheral circuit of the memory device or by an external circuit connected to the memory device.
As one solution to avoid the excess erasure of the stacked gate memory cells, split gate memory cells have been developed. International Patent Publication No. WO92/18980 discloses a flash EEPROM that uses split gate type memory cells.
FIG. 10 shows a cross section of a part of the memory cell array of a flash EEPROM using conventional split gate memory cells. The memory cell array 152 comprises a plurality of split gate memory cells (split gate transistors) 1 formed on a P type single crystalline silicon substrate 2. Each memory cell 1 has a source region 3, a drain region 4, a channel region 5, a floating gate electrode 7 and a control gate electrode 9.
Formed on the P type single crystalline silicon substrate 2 are the source region 3 and drain region 4 both of an N type. The floating gate electrode 7 is formed over the channel region 5, defined between the source region 3 and drain region 4, via a gate insulator film 6 formed of a silicon oxide film. The control gate electrode 9 is formed over the floating gate electrode 7 via an insulator film 19 and a tunnel insulator film 8, which are formed by LOCOS (Local Oxidation on Silicon).
The control gate electrode 9 does not entirely overlap the floating gate electrode 7. As one sees the gate electrodes 7 and 9 from above the substrate 2, substantially half of the floating gate electrode 7 protrudes sideways from the control gate electrode 9. Projections 7a are formed at both ends of the upper portion of the floating gate electrode 7 at the same time as the insulator film 19 is formed.
A part of the control gate electrode 9 is arranged over the channel region 5 via the insulator films 6 and 8 to constitute a select gate 10. The select gate 10, together with the source region 3 and the drain region 4, forms a select transistor 11. In the split gate type memory cell 1, therefore, a transistor, which is formed by the gate electrodes 7 and 9 and the regions 3 and 4, is connected in series to the select transistor 11.
To suppress the occupying area on the substrate 2, two memory cells 1 (which will hereinafter be denoted as "1a" and "1b" to distinguish therebetween) share the source region 3 and their floating gate electrodes 7 and control gate electrodes 9 are arranged symmetrically with respect to that common source region 3.
A passivation film 12 is formed on the memory cells 1. Each drain region 4 is connected to a drain electrode 17 in a contact hole 16. A side wall spacer 18 comprised of an insulator film is formed on the inner wall of the contact hole 16.
FIG. 11 shows the general structure of a flash EEPROM 151 using the split gate memory cells 1. The memory cell array 152 has a plurality of memory cells 1 arranged in a matrix form. The control gate electrodes 9 of a row of memory cells 1 form a single word line WLa, WLb, . . . or WLz per row. The drain electrodes 17 of a column of memory cells 1 form a single bit line BLa, BLb, . . . or BLz per column.
The individual memory cells 1b connected to each odd word line (WLa, . . . , WLm, . . . , WLy) and the individual memory cells 1a connected to each even word line (WLb, . . . , WLn, . . . , WLz) share their associated source regions 3, which form a plurality of source lines RSLa to RSLm. For example, the memory cells 1b connected to the word line WLa and the memory cells 1a connected to the word line WLb share their source regions 3, which form the source line RSLa. The individual source lines RSLa-RSLm are connected to a common source line SL.
The individual word lines WLa-WLz are connected to a row decoder 153, and the individual bit lines BLa-BLz are connected to a column decoder 154. A row address and a column address, which have been designated externally, are supplied to an address pin 155. The address pin 155 transfer the row address and column address to an address latch 157 via an address buffer 156. The address latch 157 transfers the latched row address to the row decoder 153 and the latched column address signal to the column decoder 154.
The row decoder 153 selects one of the word lines WLa-WLz (e.g., WLm), which is associated with the latched row address, and controls the electric potential on the selected word line WLm in accordance with each of the operation modes illustrated in FIG. 12.
The column decoder 154 selects one of the bit lines BLa-BLz (e.g., BLm), which is associated with the latched column address, and controls the electric potential on the selected bit line BLm in accordance with each operation mode shown in FIG. 12.
The common source line SL is connected to a source line bias circuit 162, which controls the electric potentials on the individual source lines RSLa-RSLm via the common source line SL in accordance with each operation mode shown in FIG. 12.
Externally specified data is supplied to a data pin 158 through which the data is transferred to the column decoder 154 via an input buffer 159. In accordance with the data, the column decoder 154 controls the electric potential on the selected one of the bit lines BLa-BLz.
Data read from an arbitrary memory cell 1 is supplied to the column decoder 154 via the associated one of the bit lines BLa-BLz. The data is then transferred from the column decoder 154 to a sense amplifier group 160 which comprises a plurality of sense amplifiers (not shown). The column decoder 154 connects the selected bit line BLm to the associated sense amplifier. The data that has been discriminated in the sense amplifier group 160 is sent out from the data pin 158 via an output buffer 161. The operations of the individual circuits 153-162 are controlled by a control core circuit 163.
The individual operation modes (the erase mode, write mode, read mode and standby mode) of the flash EEPROM 151 will now be discussed referring to FIG. 12.
(a) Erase Mode
In erase mode, the electric potentials of all the source lines RSLa-RSLm and the bit lines BLa-BLz are kept at the ground level (=0 V). A voltage of 14 to 15 V is applied to a selected word line WLm and a voltage of the ground level is applied to the other, non-selected word lines WLa-WLl and WLn-WLz. Therefore, the electric potentials of the control gate electrodes 9 of the memory cells 1 that are connected to the selected word line WLm are pulled up to 14 to 15 V.
The electrostatic capacitances between the source region 3 and substrate 2 and the floating gate electrode 7 are set significantly greater than the electrostatic capacitance between the control gate electrode 9 and the floating gate electrode 7. When the electric potential of the control gate electrode 9 is 14 to 15 V and the electric potential of the drain is 0 V, therefore, a high electric field is produced between the control gate electrode 9 and the floating gate electrode 7. Consequently, a Fowler-Nordheim (FN) tunnel current flows between both gate electrodes, so that electrons in the floating gate electrode 7 are drained toward the control gate electrode 9, as indicated by an arrow A in FIG. 10. As a result, data stored in the memory cells 1 is erased.
As the electrons in the floating gate electrode 7 travel toward the control gate electrode 9, the electrons jump out from the projections 7a. This facilitates the electron migration so that the electrons in the floating gate electrode 7 can be drained efficiently. This erasure is performed on all the memory cells 1 that are connected to the selected word line WLm.
(b) Write Mode
In write mode, the electric potential on the bit line BLm that is connected to the drain region 4 of the selected memory cell 1 is set to the ground level. A voltage of 4 V is applied to the other, non-selected bit lines BLa-BLl and BLn-BLz. A voltage of 2 V is applied to the word line WLm that is connected to the control gate electrode 9 of the selected memory cell 1, and the voltage of the ground level is applied to the other, non-selected word lines WLa-WLl and WLn-WLz. A voltage of 12 V is applied to all the source lines RSLa-RSLm.
The threshold voltage, Vth, of the select transistor 11 of each memory cell 1 is 0.5 V. In the selected memory cell 1, therefore, the electrons in the drain region 4 travel into the channel region 5, the conductivity of which has been inverted to an N type from a P type. Accordingly, the cell current flows toward the drain region 4 from the source region 3.
A voltage of 12 V is applied to the source region 3. Therefore, the electric potential of the floating gate electrode 7 is pulled up by the capacitive coupling between the source region 3 and the floating gate electrode 7, thus producing a high electric field between the channel region 5 and the floating gate electrode 7. Thus, the electrons in the channel region 5 are accelerated to become hot electrons, which are supplied to the floating gate electrode 7 as indicated by an arrow B in FIG. 10. Consequently, charges are stored in the floating gate electrode 7 of the selected memory cell 1 and 1-bit data is written and stored there. Unlike the erasure, this write operation can be executed for each selected memory cell 1.
(c) Read Mode
In read mode, a voltage of 4 V is applied to the word line WLm that is connected to the control gate electrode 9 of the selected memory cell 1, and the voltage of the ground level is applied to the other, non-selected word lines WLa-WLl and WLn-WLz. A voltage of 2 V is applied to the bit line BLm that is connected to the drain region 4 of the selected memory cell 1, and the voltage of the ground level is applied to the other, non-selected bit lines BLa-BLl and BLn-BLz.
As mentioned earlier, electrons are drained from the floating gate electrode 7 of a data-erased memory cell 1. Further, electrons are supplied into the floating gate electrode 7 of a data-written memory cell 1. Therefore, the channel region 5 directly below the floating gate electrode 7 of the data-erased memory cell 1 is conducting or is enabled, and the channel region 5 directly below the floating gate electrode 7 of the data-written memory cell 1 is not conducting or is disabled. Thus, the cell current that flows toward the source region 3 from the drain region 4 when 4 V is applied to the control gate electrode 9 is greater for the data-erased memory cell 1 than for the data-written memory cell 1.
As the level of the cell current flowing in each memory cell 1 is discriminated by the associated sense amplifier in the sense amplifier group 160, the value of data in the data-erased memory cell 1 can be read. For example, a data value is read with "1" as the data value in the data-erased memory cell 1 or "0" as the data value in the data-written memory cell 1. In this manner, binary data having a data value "1" indicating the erased state and a data value "0" indicating the written state can be stored in each memory cell 1.
(d) Standby Mode
In standby mode, the voltage of the ground level is applied to the common source line SL, all the word lines WLa-WLz and all the bit lines BLa-BLz. In this standby mode, no operation is performed to any memory cell 1.
Since the select transistors 11 are provided in the flash EEPROM using the thus constituted split gate memory cells, each memory cell can self-select its ON/OFF state. That is, the select transistor 11 provided in each memory cell 1 allows the memory cell to select its own conductive/non-conductive state.
Even if charges are excessively drained from the floating gate electrode 7 at the time of data erasure, therefore, the channel region 5 can be rendered non-conductive by the select gate 10. Thus, excessive erasure, if it occurs, does not raise any problem because the conductive/non-conductive states of the memory cells 1 can be controlled by the select transistors 11.
U.S. Pat. No. 5,029,130 discloses another flash EEPROM in which the source region 3 of the split gate memory cell 1 shown in FIG. 10 is changed to a drain region while the drain region 4 of the memory cell 1 is changed to a source region. FIG. 13 is a cross-sectional view showing a part of the memory cell array of a flash EEPROM using such modified memory cells 21. FIG. 14 illustrates the general structure of a flash EEPROM 171, which uses the memory cells 21. FIG. 15 shows voltages at the individual sections of the flash EEPROM 171 in individual operation modes.
The split gate memory cell 21 in FIG. 13 differs from the split gate memory cell 1 in FIG. 10 in that the source region and the drain region of the former memory cell 21 are respectively called the drain region and the source region in the latter memory cell 1. That is, the source region 3 of the memory cell 21 is called the drain region 4 in the memory cell 1, and the drain region 4 of the memory cell 21 is called the source region 3 in the memory cell 1.
The flash EEPROM 171 in FIG. 14 differs from the flash EEPROM 151 in FIG. 11 in that the common source line SL is grounded. In any operation mode, therefore, the electric potentials of the individual source lines RSLa-RSLm are held at the ground level via the common source line SL.
In write mode, 12 V is applied to the bit line BLm that is connected to the drain region 4 of the selected memory cell 21, while the electric potentials of the other, non-selected bit lines BLa-BLl and BLn-BLz are set to the ground level.
For each memory cell 21 in FIG. 13, the threshold voltage Vth of the select transistor 11 is also 0.5 V. In the selected memory cell 21, therefore, the electrons in the source region 3 travel into the channel region 5, the conductivity of which has been inverted. Accordingly, the cell current flows toward the source region 3 from the drain region 4.
As 12 V is applied to the drain region 4, the electric potential of the floating gate electrode 7 is pulled up by the capacitive coupling between the drain region 4 and the floating gate electrode 7. Consequently, a high electric field is generated between the channel region 5 and the floating gate electrode 7. The electrons in the channel region 5 are thus accelerated to become hot electrons, which are supplied to the floating gate electrode 7 as indicated by an arrow B in FIG. 13. As a result, charges are stored in the floating gate electrode 7 of the selected memory cell 21, and 1-bit data is written and stored there.
As the memory capacity of semiconductor memories is increasing recently, there is a demand for further miniaturization of the above-described split gate memory cells 1 and 21. The miniaturization of the memory cells can be accomplished by simply reducing the dimensions of the individual sections without altering their shapes. This scheme is however limited taking the processing performance of the manufacturing machines which are being developed at present into consideration.